The present invention relates to a semiconductor device having a field effect transistor of insulated gate type and a fabrication process therefor.
FIG. 9(a) is a plan view illustrating a conventional field effect transistor of insulated gate type (hereinafter referred to as "MOSFET"), and FIG. 9(b) is a sectional view taken along a line X--X in FIG. 9(a). Referring to FIGS. 9(a) and 9(b), the MOSFET includes: source and drain regions each comprised of a diffusion layer 25 which is formed within a well 23 in a surface portion of a semiconductor substrate 21 by diffusing an impurity therein and has a conductivity type different from that of the well 23; and a channel region disposed below a gate electrode 27 between the source and drain regions in the surface portion of the semiconductor substrate 21.
The diffusion layer 25 is electrically connected to an interconnection layer 30 which has a greater conductivity than the diffusion layer 25 and a low resistance and exhibits a low capacitance with the semiconductor substrate. The gate electrode 27 to be disposed on the semiconductor substrate 21 with intervention of a gate insulation film 26 is formed of a lamination of polycrystalline silicon and a high melting-point metal or a high melting-point metal compound for reduction of the resistance thereof.
The MOSFET is typically fabricated in the following manner. The gate insulation film 26 is formed on the semiconductor substrate 21 formed with a LOCOS oxide film 28 in a predetermined region thereof. Thereafter, a gate electrode material is deposited on the resulting substrate and patterned to form the gate electrode 27. In turn, ions are implanted into a surface portion of the semiconductor substrate 21 self-aligned with the gate electrode 27 by using the gate electrode 27 as a mask to form the diffusion layer 25 for the source and drain regions.
As shown in FIG. 9(a), the gate electrode 27 is used as an interconnection layer. Therefore, the gate electrode 27 which extends to another MOSFET is electrically connected to another interconnection layer 30 in a region other than the channel region via a contact hole 32 formed in an interlayer insulation film 29.
Subsequently, the entire surface of the resulting semiconductor substrate 21 is coated with an overcoat layer 31 to complete the MOSFET.
FIG. 10(a) illustrates a conventional layout of two MOSFETs connected to each other. FIGS. 10(b) and 10(c) are sectional view taken along lines X--X and Y--Y, respectively, in FIG. 10(a). As shown in FIGS. 10(a) and 10(b), the LOCOS oxide film is typically used for element isolation of the two MOSFETs.
In the prior art, the gate electrode 27 is formed on the element isolation region as well as on the channel region as shown in FIGS. 9(a) and 10(a), and used as an interconnection layer for interconnecting the gates of the MOSFETs.
The element isolation is typically achieved by way of selective oxidation by an LOCOS method known in the art. However, a bird beak is produced, thereby hindering device micronization. Level differences produced by an LOCOS oxide film 28 as shown in FIG. 10(c) may cause the breakage or a short of the interconnection layer of the gate electrode 27 formed on the LOCOS oxide film 28.
To solve the aforesaid problem associated with the element isolation by the LOCOS method, the provision of an ion-implanted region is proposed for the element isolation. Instead of the LOCOS oxide film 28 shown in FIG. 10(c), a film is formed along with the gate insulation film 26 on the semiconductor substrate, and an ion-implanted region for element isolation is formed below the film. This means that the gate electrode is also formed on the ion-implanted region with intervention of the gate insulation film.
Therefore, the gate capacitance introduced between the gate electrode and the semiconductor substrate cannot be ignored. As the semiconductor device is further micronized and has a thinner gate insulation film, the gate capacitance is remarkably increased. Further, an element isolation withstand voltage may be reduced due to an influence of a voltage applied to the interconnection layer of the gate electrode present on the ion-implanted region. Therefore, the amount of ions to be implanted into the region has to be increased to increase the element isolation withstand voltage. This reduces a junction withstand voltage, thereby further increasing the parasitic capacitance.
In case of a complementary MOSFET, as shown in FIGS. 11(a) and 11(b), gate electrodes 27 can be formed as extending across an N-channel MOSFET 43 in a P-type well 41, and a P-channel MOSFET 42 in an N-type well 40 with an LOCOS oxide film 28 is provided on a semiconductor substrate.
Where the element isolation is achieved by forming an ion-implanted region instead of the LOCOS oxide film 28 as shown in FIG. 12(a), however, there exists only a thin gate insulation film 26 between the gate electrode 27 and the semiconductor substrate. The gate electrode 27 extends from the P-channel MOSFET 42 to the N-channel MOSFET 43 beyond the boundary of the N-type well 40 and the P-type well 41. The relationship between the channel inversion voltage and the impurity concentration in a surface portion of a well is shown in FIG. 12(b). FIG. 12(b) indicates that the direction of current flow in the surface portion of the well may be inverted depending on a voltage applied to the gate electrode, and as a result, a leakage current path is produced. This undermines the reliability of the semiconductor device.
Where two gate electrodes 27 are disposed side by side in a conventional MOSFET as shown in FIG. 2(b), it is impossible for structural reasons to form an interconnection layer extending across source and drain regions. Therefore, the gate electrodes 27 must be connected to the interconnection layer 30 in a region other than a diffusion region. This limits the flexibility of device layout.
To meet the need for semiconductor device micronization, the length of a gate may be reduced to less than 0.5 .mu.m, for example. MOSFET using a conventional gate self-alignment method makes it difficult to ensure an alignment margin on the gate electrode having a length of less than 0.5 .mu.m in order to form a contact hole on the gate.